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 MantasMikaitis [    PHRhYmxlIGNsYXNzPSJ0d3BvcHVwIj48dHI+PHRkIGNsYXNzPSJ0d3BvcHVwLWVudHJ5dGl0bGUiPkdyb3Vwczo8L3RkPjx0ZD51c2VyPGJyIC8+YnVyZWF1Y3JhdDxiciAvPmVkaXRvcjxiciAvPnN5c29wPGJyIC8+PC90ZD48L3RyPjwvdGFibGU+] (talk | contribs) |
MantasMikaitis [PHRhYmxlIGNsYXNzPSJ0d3BvcHVwIj48dHI+PHRkIGNsYXNzPSJ0d3BvcHVwLWVudHJ5dGl0bGUiPkdyb3Vwczo8L3RkPjx0ZD51c2VyPGJyIC8+YnVyZWF1Y3JhdDxiciAvPmVkaXRvcjxiciAvPnN5c29wPGJyIC8+PC90ZD48L3RyPjwvdGFibGU+] (talk | contribs) No edit summary |
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*[[Background_Material_On_Verilog | Background material on Verilog]] | *[[Background_Material_On_Verilog | Background material on Verilog]] | ||
*[[More_Verilog_Parallelism_Synthesis_FSM_Implementation | Parallelism, Coding style and FSMs in Verilog]] | *[[More_Verilog_Parallelism_Synthesis_FSM_Implementation | Parallelism, Coding style and FSMs in Verilog]] | ||
==Play Area - messing with the look and feel of the opening page == | ==Play Area - messing with the look and feel of the opening page == | ||
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| title1 = CAD Tools | | title1 = CAD Tools | ||
| image1 = Apps-utilities-system-monitor-icon.png | | image1 = Apps-utilities-system-monitor-icon.png | ||
| left1 = | | left1 = [[Cadence tools |Cadence Tools]] | ||
| left2 = [[Simulation | Simulation]] | |||
| left3 = [[Synthesis | Synthesis]] | |||
| more1 = :Category:CAD | | more1 = :Category:CAD | ||
| title2 = Logic Design | | title2 = Logic Design | ||
| image2 = Crystal Clear app help index.png | | image2 = Crystal Clear app help index.png | ||
| right1 = [[Boolean Logic | Boolean Logic]] | |||
| right1 = | | right2 = [[Logic Design | Logic design]] | ||
| right3 = [[Combinatorial | Combinatorial Logic]] | |||
| more2 = :Category:Logic | |||
}}{{MenuBox linkbox | }}{{MenuBox linkbox | ||
| title1 = Verilog | | title1 = Verilog | ||
| image1 = Crystal Clear app help index.png | | image1 = Crystal Clear app help index.png | ||
| | | left1 = [[HDLs | About Hardware Description Languages in general]] | ||
| left2 = [[Verilog Keywords | Verilog keywords]] | |||
| left3 = [[Verilog Operators | Verilog operators]] | |||
| more1 = :Category:Verilog | | more1 = :Category:Verilog | ||
Revision as of 12:42, 1 July 2014
Welcome to the School of CS Engineering wiki
This is the wiki created in the labs of School of Computer Science, University of Manchester by some students and engineers.
Question-Answer based Engineering material:
- Cadence Tools
- Simulation
- Synthesis
- Field Programmable Gate Arrays(FPGAs)
- Logic
- Other interesting topics
- ARM
Other material:
Play Area - messing with the look and feel of the opening page
Welcome to the School of CS Engineering Wiki
This is the homepage for the engineering activities in the School of CS. This wiki contains information on a number of engineering related subjects. The material can be used to support engineering modules in School, engineering projects, student hobby projects, or as a source of general hardware related information. The information is split up into sensible categories - where you can find general background information, examples and FAQs. If you are not sure where to look, try the search box in the top right hand corner.
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CAD Tools
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Logic Design
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Verilog
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ARM
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Arduino
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Hardware Projects Support
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