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Interesting Engineering Questions Answered
 MantasMikaitis [    PHRhYmxlIGNsYXNzPSJ0d3BvcHVwIj48dHI+PHRkIGNsYXNzPSJ0d3BvcHVwLWVudHJ5dGl0bGUiPkdyb3Vwczo8L3RkPjx0ZD51c2VyPGJyIC8+YnVyZWF1Y3JhdDxiciAvPmVkaXRvcjxiciAvPnN5c29wPGJyIC8+PC90ZD48L3RyPjwvdGFibGU+] (talk | contribs)No edit summary |
MantasMikaitis [PHRhYmxlIGNsYXNzPSJ0d3BvcHVwIj48dHI+PHRkIGNsYXNzPSJ0d3BvcHVwLWVudHJ5dGl0bGUiPkdyb3Vwczo8L3RkPjx0ZD51c2VyPGJyIC8+YnVyZWF1Y3JhdDxiciAvPmVkaXRvcjxiciAvPnN5c29wPGJyIC8+PC90ZD48L3RyPjwvdGFibGU+] (talk | contribs) No edit summary |
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| right1 = [[Boolean Logic | Boolean Logic]] | | right1 = [[Boolean Logic | Boolean Logic]] | ||
| right2 = [[Logic Design | Logic design]] | | right2 = [[Logic Design | Logic design]] | ||
| right3 = [[Logic_Questions | Logic Design FAQ]] | | right3 = [[Combinatorial | Combinatorial Logic]] | ||
| right4 = [[Sequential | Sequential Logic]] | |||
| right5 = [[FSMs | Finite State Mashines]] | |||
| right6 = [[Logic_Questions | Logic Design FAQ]] | |||
}}{{MenuBox linkbox | }}{{MenuBox linkbox | ||
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| left2 = [[:Category:VerilogKeywords | Verilog Keywords]] | | left2 = [[:Category:VerilogKeywords | Verilog Keywords]] | ||
| left3 = [[Verilog Operators | Verilog operators]] | | left3 = [[Verilog Operators | Verilog operators]] | ||
| left4 = [[Verilog Module | Modules]] | |||
| left5 = [[Behavioural and Structural | Behavioural vs structural Verilog]] | |||
| left6 = [[Verilog System Tasks and Functions | System functions]] | |||
| left7 = [[Verilog Tasks and Functions | Tasks and functions]] | |||
| left8 = [[Testbenches | How to create a testbench for simulation]] | |||
| left9 = [[Verilog Examples and Questions | Examples and Questions]] | |||
| title2 = ARM | | title2 = ARM | ||
| image2 = Cpu-ARM-icon.png | | image2 = Cpu-ARM-icon.png | ||
| right1 = [[ARM | Frquently asked questions about ARM]] | | right1 = [[ARM | Frquently asked questions about ARM]] | ||
| right2 = | | right2 = | ||
}} | }} | ||
{{MenuBox linkbox | {{MenuBox linkbox | ||
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| image1 = PCB-icon.png | | image1 = PCB-icon.png | ||
| left1 = [[Parentie And Komodo | Parentie/Komodo]] | | left1 = [[Parentie And Komodo | Parentie/Komodo]] | ||
| left2 = [[ | | left2 = [[Lab Tools Integration | Tools integration]] | ||
| left3 = [[Lab Board | Engineering lab board]] | | left3 = [[Lab Board | Engineering lab board]] | ||
| left4 = [[FPGAs | FPGAs]] | |||
| title2 = MU0 and Stump | | title2 = MU0 and Stump | ||
Revision as of 10:57, 2 July 2014
Welcome to the School of CS Engineering Wiki
This is the homepage for the engineering activities in the School of CS. This wiki contains information on a number of engineering related subjects. The material can be used to support engineering modules in School, engineering projects, student hobby projects, or as a source of general hardware related information. The information is split up into sensible categories - where you can find general background information, examples and FAQs. If you are not sure where to look, try the search box in the top right hand corner.
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CAD Tools
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Logic Design
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Verilog
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ARM
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Laboratory Equipment
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MU0 and Stump
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Arduino
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Hardware Projects Support
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